The invention relates generally to memory management in a computer system and more specifically to a method and apparatus for performing a memory access operation in a computer system.
In a computer system, instructions and data are stored in a memory device until they are needed. The memory device is organized according to an addressing scheme to allow the instructions and data to be located by specifying an address. However, while the memory device is organized into a plurality of physical addresses, it is often useful for a processor to consider the instructions and data to be organized according to a different addressing scheme, denoted by virtual addresses. The virtual addresses may be converted to physical addresses to allow the instructions and data to be accessed in the memory device.
A translation lookaside buffer (TLB) structure may be used to provide a cache for translation of virtual addresses to physical addresses. The TLB structure includes a plurality of page directories that contain page directory entries and a plurality of page tables that contain page table entries. The page directory entries serve as pointers to the plurality of page tables and the page table entries serve as pointers to pages of data in the memory device.
FIG. 6 is a block diagram illustrating the relationship between a processor, a TLB structure, and memory. Processor 601 is coupled to and communicates in virtual addresses with TLB structure 602. TLB structure 602 is coupled to and communicates in physical addresses with memory device 603.
FIG. 1 is a flow diagram illustrating a prior art process for obtaining data from a TLB structure. In step 101, a page directory entry is read from a page directory. In step 102, a page table entry is read from a page table using the page directory entry. In step 103, data are read from a page in the memory device using the page table entry.
While a TLB structure is useful for caching virtual address-to-physical address translations, it is not readily compatible with a computer architecture that provides for the emulation of an emulated processor using a native processor. The native processor is the processor actually present in the system, while the emulated processor is a processor whose performance characteristics simulated by the native processor. The emulation allows execution on the native processor of software programmed to be executed on a processor of the same type as the emulated processor. However, software programmed to be executed on a processor of the same type as the emulated processor is subject to the constraints and conditions associated with that type of processor. For example, the emulated processor architecture may already use all of its address space thereby causing incompatibility with certain bookkeeping techniques commonly used with prior art TLBs. Thus, a method and apparatus is needed to allow efficient memory accesses given the constraints imposed by an emulated processor architecture.